drone
Multi-Chip Avionics Stack
Three-layer heterogeneous compute: AI inference, FPGA sensor fusion, MCU safe-landing autonomy.
Reference avionics package embodying graceful degradation: Jetson Orin NX 16 GB (~100 TOPS, 10–25 W), Xilinx Zynq UltraScale+ ZU3EG (EKF <1 ms), STM32H7 flight-layer watchdog with NVM Return-to-Home.
Layer 1 executes compressed Tiny AI (YOLOv8n / MobileNetV3-Small, INT8) with inference <100 ms and model size <20 MB.
Layer 2 guarantees deterministic EKF fusion in FPGA fabric independent of OS jitter.
Layer 3 isolates flight safety: if both upper layers fail, MCU lands the aircraft from non-volatile memory.
Source: SWARMind Drones Proposal Draft § Multi-Chip Architecture.
Layer 2 guarantees deterministic EKF fusion in FPGA fabric independent of OS jitter.
Layer 3 isolates flight safety: if both upper layers fail, MCU lands the aircraft from non-volatile memory.
Source: SWARMind Drones Proposal Draft § Multi-Chip Architecture.
Mission profile
Embedded on each swarm node; laboratory gate requires physical layer-disconnect demonstrations of expected survival behaviour.